1. Field of the Invention
The invention relates to computer techniques, and more particularly to program instruction rearrangement methods.
2. Description of the Related Art
A processor typically utilizes pipelining techniques to simultaneously execute multiple instructions. When an executed instruction in a pipeline uses an operand register which is the output of a former instruction, execution of the instruction is suspended until the former instruction yields the result. An example is given with reference to the following instructions:                #101 . add a x y        #102 . inc a        #103 . dec b        //a=(x+y)+1; b=b−1        
With reference to FIG. 1, execution stages of instruction #101 may be classified as:                Fetch instruction #101;        Read x and y;        Add; and        Write to a.        
Instruction #102 is fetched in the second stage, followed by the third stage for reading register a, but instruction #101 writes the result thereof to register a at the fourth stage, thus instruction #102 is not able to read register a until the fifth stage. In other words, the input of instruction #102 at the fifth stage depends on the output of instruction #101 at the fourth stage. Additionally, at the fifth stage of instruction #102 , instruction #103 is also executed. A total of 8 clocks are required to execute instructions #101˜103. If the register read by instruction #102 in the fifth stage is not the register a, because no dependency exists between instruction #102 and the fourth stage of instruction #101 , instruction #102 can read register a at the third stage, and instruction #103 can step two stages forward, thus, just a total of 6 clocks are required to execute instructions #101˜103.
As can be appreciated through the described example, if not properly arranged, two instructions with dependencies in a pipeline of a processor may reduce execution efficiency.